1. Field of the Invention
The present invention relates to an image processing apparatus, a control method thereof, and a storage medium.
2. Description of the Related Art
A reconfigurable circuit such as a programmable logic device (PLD) or a field programmable gate array (FPGA) capable of changing the configuration of a logic circuit is well known. Generally, changing the configuration of a logic circuit of the PLD or the FPGA is achieved by writing circuit configuration information stored in a non-volatile memory such as a ROM into a configuration memory, which is a volatile memory included in the PLD or the FPGA, at the time of activation. Also, the information stored in the configuration memory is cleared when power is turned off, and it is therefore necessary to again write the circuit configuration information stored in the ROM into the configuration memory when power is turned on. The method as described above that changes the logic circuit of the PLDs or the FPGAs only once during power supply is called “static reconfiguration”. In contrast, development has been underway to provide an FPGA or the like that is capable of dynamically changing the configuration of a logic circuit during operation of the logic circuit, and such a method that dynamically changes the logic circuit is called “dynamic reconfiguration”.
There is an FPGA capable of not only rewriting the circuit configuration of the entire chip of the FPGA, but also rewriting only the circuit configuration of a specific area in the chip. Such rewriting is called “partial reconfiguration”. Particularly, changing the configuration of the circuitry on the chip excluding the circuit that is in operation without stopping the operation of that circuit is called “dynamic partial reconfiguration”. In the dynamic partial reconfiguration, unlike the dynamic reconfiguration that rewrites the entire configuration memory, only a partial area in the configuration memory is rewritten. Accordingly, the logic circuit of the FPGA can be partially reconfigured. By using the dynamic partial reconfiguration described above, it is possible to, for example, mount a plurality of logic circuits in a specific area in an FPGA, and switch the logic circuits on a time shared basis. As a result, various functions that can fit for various applications can be flexibly implemented with the use of a fewer hardware resources while maintaining high-speed computing performance of hardware.
However, although the circuit configuration can be changed during operation, a long period of time is required to change (rewrite) the circuit configuration, and the time length is proportional to the size of logic circuit configuration information written into the configuration memory. To address this, techniques have been proposed to reduce the rewriting time required to rewrite the circuit configuration.
Japanese Patent Laid-Open No. 2012-234337 discloses a technique for reducing the conventional rewriting time by predicting processing that is very likely to be processed next during image processing, and loading in advance config data for implementing the predicted processing into a high-speed configuration memory. As a result of loading config data in advance, it is possible to shorten the loading time required to load the circuit configuration data during image processing, and achieve a faster image processing speed.
With an image processing apparatus such as a multi-function printer (MFP), a selection can be made from among a plurality of processing operations (copy job, print job, send job, and the like) in response to a request from the user, and each image processing is implemented by hardware or software. In addition, MFPs available in recent years have a power saving state from the viewpoint of reducing power consumption, and also have a function of making a transition to the power saving state when no access is made to the MFP for a fixed period of time and recovering from the power saving state when the MFP is used again. Particularly, demand is increasing for reducing the recovery period required to recover from the power saving state as short as possible so as to provide fast availability of the MFP and enhance usability for the user.
However, the conventional technique described above has the following problems. For example, if the reconfiguration technique is applied to an image processing unit provided in an image processing apparatus, it is possible to speed up the rewriting time required to rewrite the config data during image processing. However, if the user makes a setting change, the content of processing to be performed by the image processing unit is not fixed until a request to start the processing is received from the user. Accordingly, with the above-described conventional technique, the config data is loaded after the user issues a request to start processing and the content of processing is fixed. For this reason, the time required to start processing is not accelerated.